The present invention relates to a semiconductor device and a technique of manufacturing the same. More particularly, it relates to a technique which is effectively applicable when electrically coupling a semiconductor chip with an external circuit.
When building an LSI of a ball grid array structure, it is possible for the LSI to assume the configuration of a BGA (Ball Grid Array) type, a CSP using a rewiring structure, or a bump electrode structure.
Wire bonding as a package is required in the BGA type, and rewiring of semiconductor chips on a passivation film is required in the rewiring structure. These are coupled to pads provided in an IO region of the LSI chip.
On the other hand, as for the bump electrode structure, on the uppermost metal wiring layer in the LSI chip, coupling to balls making up the bump electrode is made. Therefore, the power-supply wiring and GND wiring are directly coupled to the lower wiring layer without using an IO cell, having a structure without pads.
As described above, a layout of the BGA type as well as the rewiring structure and that of the bump electrode structure are different. Therefore, when the above two package structures are provided on the same LSI, exclusive masks for providing opening in the uppermost-layer wiring must be prepared separately.
Japanese Unexamined Patent Publication No. 2003-273154 (Patent Document 1) discloses a technique as follows. That is, first, near four corners of a surface of the active device in a semiconductor-chip region, there is formed a metal wiring layer having both a pad region for wire bonding and a pad region for rewiring. Furthermore, a surface of the metal wiring layer is covered with a passivation film. Then, in accordance with the packaged state of the semiconductor chip, the passivation film on either the pad region for wire bonding or the pad region for rewiring is selectively removed to allow opening. The above technique makes it possible to allow the semiconductor chip to cope with a package with lead terminals or a CSP (Chip Size Package) without raising a cost and increasing the size of the semiconductor device.
According to a technique disclosed in Japanese Unexamined Patent Publication No. 11-87400 (Patent Document 2), there is formed an integrated circuit on a semiconductor chip, which has pad parts for electrically coupling the integrated circuit with an external circuit. Each of the pad parts is provided with two junctions including openings selectively formed in protective films which cover the pad parts. With this structure, the integrated circuit can be electrically coupled to the external circuit either by use of wire bonding or by use of bump electrodes, thereby improving development efficiency and mass production efficiency of the semiconductor device.
(Patent Document 1)
    Japanese Unexamined Patent Publication No. 2003-273154(Patent Document 2)    Japanese Unexamined Patent Publication No. Hei 11 (1999)-87400